The present invention relates to memory integrated circuits, and more particularly to a magnetic random access memory cell adapted to store differential data.
Semiconductor memory devices have been widely used in electronic systems to store data. There are generally two types of semiconductor memories, including non-volatile and volatile memories. A volatile memory device, such as a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM) device, loses its data when the power applied to it is turned off. In contrast, a non-volatile semiconductor memory device, such as a Flash Erasable Programmable Read Only Memory (Flash EPROM) or a magnetic random access memory (MRAM), retains its charge even after the power applied thereto is turned off. Therefore, where loss of data due to power failure or termination is unacceptable, a non-volatile memory is used to store the data.
FIG. 1A is a simplified cross-sectional view of a magnetic tunnel junction (MTJ) structure 10 used in forming a spin torque transfer (STT) MRAM cell. MTJ 10 is shown as including, in part, a reference layer 12, a tunneling layer 14, and a free layer 16. Reference layer 12 and free layer 16 are ferromagnetic layers. Tunneling layer 14 is a nonmagnetic layer. The direction of magnetization of reference layer 12 is fixed and does not change. The direction of magnetization of free layer 16, however, may be varied by passing a sufficiently large current through the MTJ structure. In FIG. 1A, reference layer 12 and free layer 14 are assumed to have the same magnetization direction, i.e., they are in a parallel state. In FIG. 1B, reference layer 12 and free layer 14 are assumed to have opposite magnetization directions, i.e., they are in an anti-parallel state. In FIG. 1C, reference layer 12 and free layer 14 are assumed to have the same magnetization direction perpendicular to a plane defined by the interface of free layer 16 and tunneling layer 14. In FIG. 1D, reference layer 12 and free layer 14 are assumed to have opposite magnetization directions perpendicular to a plane defined by the interface of free layer 16 and tunneling layer 14.
To switch from the parallel state, as shown in FIG. 1A, to the anti-parallel state, as shown in FIG. 1B, the voltage potential of reference layer 12 is increased relative to that of free layer 16. This voltage difference causes spin polarized electrons flowing from free layer 16 to reference layer 12 to transfer their angular momentum and change the magnetization direction of free layer 16 to the anti-parallel state, as shown in FIG. 1B. To switch from the anti-parallel state to the parallel state, the voltage potential of free layer 16 is increased relative to that of reference layer 12. This voltage difference causes spin polarized electrons flowing from reference layer 16 to free layer 12 to transfer their angular momentum and change the magnetization direction of free layer 16 to the parallel state, as shown in FIG. 1A.
To switch from the parallel state to the non-parallel state or vice versa, the voltage applied to MTJ 10 and the corresponding current flowing through MTJ must be greater than a respective pair of threshold values. The voltage that must exceed a threshold voltage in order for the switching to occur is also referred to as the switching voltage Vc. Likewise, the current that must exceed a threshold current in order for the switching to occur is referred to as the switching current Ic. As is well known, when free layer 16 and reference layer 12 have the same magnetization direction (parallel state), MTJ 10 has a relatively low resistance. Conversely, when free layer 16 and reference layer 12 have the opposite magnetization direction (anti-parallel state), MTJ 10 has a relatively high resistance. Due to the physical properties of an MTJ, the critical current required to change the state of an MTJ from a parallel to an anti-parallel is often greater than the critical current required to change the state of the MTJ from an anti-parallel to a parallel state.
FIG. 2A shows an MTJ 10 and an associated select transistor 20 together forming an STT-MRAM cell 30. Transistor 20 is often an NMOS transistor due to its inherently higher current drive, lower threshold voltage, and smaller area relative to a PMOS transistor. As is described further below, the current used to write a “1” in STT-MRAM 30 is different than the current used to write a “0”. The asymmetry in the direction of current flow during these two write conditions is caused by the asymmetry in the gate-to-source voltage of transistor 20. Accordingly, a write driver circuit adapted to deliver sufficient current to write a “0”, may not be able to provide enough current to write a “1”. Similarly, a write driver circuit adapted to deliver sufficient current to write a “1” may deliver a current that is greater than what would otherwise be an acceptable current level to write a “0”.
In the following description, an STT-MRAM cell is defined as being in a logic “0” state when the free and reference layers of its associated MTJ are in a parallel (P) state, i.e., the MTJ exhibits a low resistance. This low resistance state is also alternatively shown as Rlow or RP state Conversely, an STT-MRAM cell is defined as being in a logic “1” state when the free and reference layers of its associated MTJ are in an anti-parallel (AP) state, i.e., the MTJ exhibits a high resistance. This high resistance state is also alternatively shown as Rhigh or RAP state. Furthermore, in the following, it is assumed that the reference layer of the MTJ faces its associated select transistor, as shown in FIG. 2A. Therefore, in accordance with the discussion above, a current flowing along the direction of arrow 35 (the up direction) (i) either causes a switch from the P state to the AP state thus to write a “1”, (ii) or stabilizes the previously established AP state of the associated MTJ. Likewise, a current flowing along the direction of arrow 40 (the down direction) (i) either causes a switch from the AP state to the P state thus to write a “0”, (ii) or stabilizes the previously established P state of the associated MTJ. It is understood, however, that in other embodiments this orientation may be reversed so that the free layer of the MTJ faces its associated select transistor. In such embodiments (not shown), a current flowing along the direction of arrow 35 (i) either causes a switch from the AP state to the P, (ii) or stabilizes the previously established P state of the associated MTJ. Likewise, in such embodiments, a current flowing along the direction of arrow 40 (i) either causes a switch from the P state to the AP state, (ii) or stabilizes the previously established AP state. FIG. 2B is a schematic representation of STT-MRAM 30 of FIG. 2A in which MTJ 10 is shown as a storage element whose resistance varies depending on the data stored therein. The MTJ changes its state (i) from P to AP when the current flows along arrow 35, and (ii) from AP to P when the current flows along arrow 40.
As described above, the voltage required to switch an MTJ from an AP sate to a P state, or vice versa, must exceed a critical value Vc. The current corresponding to this voltage is referred to as the critical current Ic. FIG. 3 represents the variation in the MTJ state (or its resistance) during various write cycles. To transition from the P state (low resistance state) to AP state (high resistance state), a positive voltage of Vc is applied. Once in the AP state, removing the applied voltage does not affect the state of the MTJ. Likewise, to transition from the AP state to the P state, a negative voltage of Vc is applied. Once in the P state, removing the applied voltage does not affect the state of the MTJ. The resistance of the MTJ is Rhigh when it is in AP state and receives no voltage. Likewise, the resistance of the MTJ is Rlow when it is in P state and receives no voltage.
FIG. 4A shows an MTJ 10 being programmed to switch from an anti-parallel state (i.e., high resistance state, or logic “1” state) to a parallel state so as to store a “0” (i.e., low resistance state, or logic “0” state). It is assumed that MTJ 10 is initially in a logic “1” or AP state. As described above, to store a “0”, a current Ic greater than the critical current is caused to flow through transistor 20 in the direction of arrow 40. To achieve this, one of the current carrying terminals (SL) of transistor 20 is coupled to the ground potential via a resistive path (not shown), a positive voltage Vcc is applied to the gate node (WL or wordline) of transistor 20, and a positive voltage Vcc is applied to the other current carrying terminal (BL or bitline) of transistor 20.
FIG. 4B shows an MTJ being programmed to switch from a parallel state to an anti-parallel state so as to store a “1”. It is assumed that MTJ 10 is initially in a logic “0” or P state. To store a “1”, a current Ic greater than the critical current is caused to flow through transistor 20 in the direction of arrow 35. To achieve this, node SL is supplied with the voltage Vcc via a resistive path (not shown), node WL is supplied with the voltage Vcc, and node BL is coupled to the ground potential via a resistive path (not shown). Accordingly, during a write “1” operation, the gate-to-source voltage of transistor 20 is set to (VWL−VSN), and the drain-to-source voltage of transistor 20 is set to (VSL−VSN). FIG. 5B shows an exemplary timing diagram of the voltage levels VWL, VSL, VSN, and VBL during a write “1” operation.
FIG. 5 is a schematic diagram of a portion of an array 100 of STT-MRAM cells. Array 100 is shown as including, in part, N columns, a write driver 104, and a sense amplifier 102. Three of the columns, namely columns 1, 2 and N, are shown in FIG. 5. It is understood that array 100 includes a multitude of rows only one of which is shown for simplicity. Lines (nodes) BL1 and SL1 represent the bit lines and source lines associated with the MTJ cells disposed in column 1; lines BL2 and SL2 represent the bit lines and source lines associated with the MTJ cells disposed in column 2; lines BLN and SLN represent the bit lines and source lines associated with the MTJ cells disposed in column N. Lines BL1, BL2 . . . BLN are shown as being coupled to output terminal WBL of write driver 104. Likewise, lines SL1, SL2 . . . SLN are shown as being coupled to output line WSL of write driver 104. Output terminal WBL is coupled to a first input terminal of sense amplifier 102. The second terminal of sense amplifier 102 is coupled to a reference line MREF. To select an MTJ, the row and column associated with that MTJ are activated. For example, to select MTJ 101 disposed in column 1, signal lines WL, and CS1 both receive high voltages. Likewise, to select MTJ 10N, signal lines WL, and CSN both receive high voltages.
During a read operation, write driver 104 causes line WSL to be pulled to the ground potential and line WBL to be tri-stated. This causes the current that flows through that MTJ to be sensed by sense amplifier 102. Transistor 106 provides a discharge path to ground for this current. The other input terminal of sense amplifier 102 receives a reference current Iref that corresponds to an average of a current representing a stored “1” and a current representing a stored “0”. Sense amplifier 102 compares this reference current to the current supplied by the selected MTJ to determine the data stored therein. To write to an MTJ, the bit lines and source lines associated with that MTJ are driven to the required programming voltages by write driver 104, as is known to those skilled in the art.